Hybrid resonant converter

ABSTRACT

A hybid resonant DC to DC converter uses an LLC or other resonant structure on the primary side, applying a two state waveform to one end of the resonant structure and a multi-state waveform to the other end of the resonant structure. The waveforms are at or near the resonant resonant frequency and the output voltage level is regulated by varying the shape of the multi-state waveform by varying the duty cycle of the switches used to generate it. The allows the converter to operate near or at its optimal resonant point, resulting in higher efficiency, over a wide range of regulated output voltage levels.

PRIORITY CLAIM

This application claims the benefit of U.S. Provisional Pat. App. No.,62/532,789, filed Jul. 14, 2017, which is hereby incorporated byreference.

FIELD

The following is related generally to the field of direct current todirect current (DC to DC) converters and, more specifically, to resonantconverters.

BACKGROUND

Resonant converters are a type of direct current to direct current (DCto DC) electric power converter that include a network of inductors andcapacitors tuned to resonate at a particular frequency. A resonantconverter may need to handle a wide range of input voltages and a widerange of output voltages. FIG. 1A shows an example of a resonantconverter.

In this example, the transformer T 102 has a secondary winding 103 witha center tap c connected to drive the load, represented by theresistance RL 109, with the output voltage V_(O) at an output node ofthe DC to DC converter, where V_(O) is used to represent both the outputnode and the voltage level at that node. The center tap c is alsoconnected to ground through the capacitor 105. The upper and lower tapsof the secondary winding are connected to ground though the diode D1 138on the one end and through the diode D2 139 on the other. The diodes D1138 and D2 139 can also be replaced with actively controlled MOSFETs orother switches.

On the primary side, the LLC (inductor-inductor-capacitor) elements ofthe resonant tank are the inductors Lr 131 and Lm 133 and the capacitorCr 135 that are connected in series between the node a and ground. Theinductor Lm 133 is connected in parallel with the primary winding 101 ofthe transformer T 102. In this example, the inductor Lm 133 is connectedthrough the capacitor Cr 135 on the one side, and on the other side tothe node a through the inductor Lr 131. The switches Q₁ 121 and Q₂ 122are connected between the + and − terminals of a DC input voltage sourceVin 107 and are alternately switched on to a generate two-state waveformat the node a. The switches Q₁ 121 and Q₂ 122 can be implemented asMOSFETs or other transistors, for example.

FIG. 1B shows the waveform 11 at node a. The output voltage Vo isregulated by varying the frequency of the waveform, which often differssignificantly from the resonant frequency of the resonant tank ofinductors Lr 131 and Lm 133 and the capacitor Cr 135. For example, in anapplication as a battery charger for use with an electrical vehicle, theinput voltage Vin could vary between 680-800 volts, while the DC outputvoltage Could be in the 400-750 volt range. In operating over such awide range of input and output voltages, typical resonant converters areoften far from their optimal resonant point, resulting in lowefficiency.

SUMMARY

According to one aspect of the present disclosure, there is provided anapparatus that includes a DC to DC voltage converter having an inputvoltage node configure to receive an input voltage, a first bridgecircuit, a second bridge circuit, and an intermediate circuit. The firstbridge circuit is connected to the input voltage node and a ground node,and is configured to provide a first waveform to a first internal node.The second bridge circuit connected to the input voltage node, theintermediate voltage node and the ground node, and is configured toprovide a second waveform to a second internal node, where the secondwaveform is a multi-state waveform. The intermediate circuit includes aninductor connected between the first internal node and the secondinternal node. The first inductor is configured to be driven by thefirst and second waveforms to provide an output voltage to an outputvoltage node.

Optionally, in the preceding aspect, another implementation of theaspect provides that the DC to DC voltage converter further includes atransformer having a primary coil and a secondary coil with a commoncore, wherein the output voltage node is connected to a first terminalof the secondary coil, and wherein the inductor is connected in parallelwith the primary coil.

Optionally, in the preceding aspects, another implementation of theaspect provides that the intermediate circuit is a resonant tank.

Optionally, in the preceding aspect, another implementation of theaspect provides that the resonant tank of the DC to DC voltage convertercomprises: the first inductor, a second inductor, and a first capacitorconnected in series between the first internal node and the secondinternal node.

Optionally, in any of the preceding aspects, another implementation ofthe aspect provides that the first bridge circuit of the DC to DCvoltage converter comprises: a first switch connected between the firstinternal node and the input voltage node; and a second switch connectedbetween the first internal node and the ground node.

Optionally, in any of the preceding aspects, another implementation ofthe aspect provides that in the DC to DC voltage converter the secondbridge circuit comprises: a third switch connected between the secondinternal node and the input voltage node; a fourth switch connectedbetween the second internal node and the ground node; and anintermediate voltage switch connected between the intermediate voltagenode and the second internal node.

Optionally, in the preceding aspects, another implementation of theaspect provides that in the DC to DC voltage converter the intermediatevoltage switch comprises a fifth switch and a sixth switch connected inseries between the intermediate voltage node and the second internalnode.

Optionally, in any of the preceding aspects, another implementation ofthe aspect provides that in the DC to DC voltage converter theintermediate voltage switch comprises: a fifth switch through which thethird switch is connected to the second internal node through a thirdinternal node; a sixth switch through which the fourth switch isconnected to the second internal node through a fourth internal node; afirst diode connected between the third internal node and theintermediate voltage node; and a second diode connected between thefourth internal node the intermediate voltage node.

Optionally, in any of the preceding aspects, another implementation ofthe aspect provides that in the DC to DC voltage converter theintermediate voltage switch comprises: a fifth switch through which thethird switch is connected to the second internal node through a thirdinternal node; a sixth switch through which the fourth switch isconnected to the second internal node through a fourth internal node; aseventh switch connected between the third internal node and theintermediate voltage node; and an eighth switch connected between thefourth internal node the intermediate voltage node.

Optionally, in any of the preceding aspects, another implementation ofthe aspect provides that in the DC to DC voltage converter furthercomprises a control circuit connected to the first bridge circuit andthe second bridge circuit and configured to supply thereto a set ofcontrol signals having a cycle of a first frequency. The control circuitis configured to supply a set of control signals whereby the firstbridge circuit generates the waveform to have the first frequency and tohave at least a high value and a low value, whereby the second bridgegenerates the second waveform to have the first frequency and to have atleast a high value, an intermediate value and a low value, anintermediate value and a low value, and wherein the first and secondinternal nodes are not concurrently at either of the corresponding highvalues or the corresponding low values.

Optionally, in the preceding aspects, another implementation of theaspect provides that in the DC to DC voltage converter the controlcircuit is configured to provide to the second bridge circuit controlsignals having an adjustable duty cycle, and that the control circuit isfurther configured to regulate the value of the output voltage byvarying the duration of the duty cycle while maintaining the firstfrequency.

According to another aspect of the present disclosure, there is provideda system that includes a DC to DC voltage conversion system, comprisinga DC to DC conversion circuit and a control circuit. The DC to DCconversion circuit includes an input voltage node, a first bridgecircuit, a second bridge circuit, and an intermediate circuit. The firstbridge circuit is connected to the input voltage node and a ground node,and is configured to provide a first waveform to a first internal node.The second bridge circuit connected to the input voltage node, theintermediate voltage node and the ground node, and is configured toprovide a second waveform to a second internal node, where the secondwaveform is a multi-state waveform. The intermediate circuit includes aninductor connected between the first internal node and the secondinternal node. The first inductor is configured to be driven by thefirst and second waveforms to provide an output voltage to an outputvoltage node. The control circuit is configured to supply a set ofcontrol signals whereby the first bridge circuit applies to the firstinternal node the first waveform of the first frequency and having atleast a high value and a low value, whereby the second bridge circuitapplies to the second internal node the second waveform having at leasta high value, an intermediate value and a low value, and wherein thefirst and second internal nodes are not concurrently at either of thecorresponding high values or the corresponding low values.

Optionally, in any of the preceding aspects, another implementation ofthe aspect provides that the control circuit of the system circuit isconfigured to provide to the second bridge circuit control signalshaving an adjustable duty cycle.

Optionally, in any of the preceding aspects, another implementation ofthe aspect provides that the control circuit of the system circuit isconfigured to regulate the value of the output voltage by varying theduration of the duty cycle while maintaining the first frequency.

According to an additional aspect of the present disclosure, there isprovided a method that includes generating a DC output voltage from a DCinput voltage. The method includes receiving an input voltage andgenerating a first waveform and a second waveform from the inputvoltage. The first waveform and the second waveform are respectivelyreceived at a first node and a second node of a DC to DC voltageconverter. The DC to DC voltage converter includes a resonant tankconnected between the first node and the second node and an output nodeconnected to the resonant tank. The DC to DC voltage converter generatesfrom the first and second waveforms an output voltage at the outputvoltage node. The first waveform has a cycle of a first frequency with ahigh value in a second part of the cycle and a low value in a first partof the cycle. The second waveform is a multi-level waveform of the firstfrequency with the high value for a first portion of the first part ofthe cycle and an intermediate value for a second portion of the firstpart of the cycle, and with the low value for a first portion of thesecond part of the cycle and the intermediate value for a second portionof the second part of the cycle, the intermediate value being betweenthe high value and the low value.

Optionally, in any of the preceding aspects, another implementation ofthe aspect provides that the method further includes that the firstportion of the part of the cycle is of substantially the same durationas the first portion of the second part of the cycle.

Optionally, in any of the preceding aspects, another implementation ofthe aspect provides that the method further includes regulating thevalue of the output voltage by varying a duration of the first portionof one or both of the first part of the cycle or the second part of thecycle while maintaining the first frequency.

Optionally, in any of the preceding aspects, another implementation ofthe aspect provides that the method of generating the second waveformincludes receiving first, second, third and fourth control waveforms atfirst, second, third, and fourth switches, respectively, wherein thefirst switch is connected between the input voltage and the second node,the second switch is connected between ground and the second node, andthe third and fourth switches are connected in series between the secondnode and an intermediate node configured to supply the intermediatevalue.

Optionally, in any of the preceding aspects, another implementation ofthe aspect provides that the method includes that the first and thirdcontrol waveforms are non-overlapping, the first control waveform beinghigh during the first portion of the second part of the cycle, andwherein the second and fourth control waveforms are non-overlapping, thesecond control waveform being high during the first portion of the firstpart of the cycle.

Optionally, in any of the preceding aspects, another implementation ofthe aspect provides that the method provides that the first and secondcontrol waveforms have substantially equal duty cycles and that themethod further includes regulating the value of the output voltage, theregulating including varying durations of the duty cycle of the firstand second control waveforms while maintaining the first frequency.

This Summary is provided to introduce a selection of concepts in asimplified form that are further described below in the DetailedDescription. This Summary is not intended to identify key features oressential features of the claimed subject matter, nor is it intended tobe used as an aid in determining the scope of the claimed subjectmatter. The claimed subject matter is not limited to implementationsthat solve any or all disadvantages noted in the Background.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B show a prior art example of a resonant converter and acorresponding waveform.

FIG. 2A shows an embodiment of a hybrid resonant converter system.

FIGS. 2B and 2C show embodiments of a hybrid resonant converter andcontrol block for the system of FIG. 2A.

FIG. 2D shows examples of multi-state and two-state waveforms applied tothe elements of the resonant converter of FIG. 2B.

FIG. 3 is an example of a switching sequence to generate the waveformsof FIG. 2D in the circuit of FIG. 2B.

FIGS. 4A-4D, 5A-5D and 6 are sets of waveforms showing the operation ofthe circuit of FIG. 2B for different Vin, V_(O) combinations.

FIG. 7 is a flow chart illustrating aspects of the operation for oneembodiment of the system of FIG. 2A.

FIGS. 8A, 8B, 9A and 9B look at embodiments of the DC to DC voltageconverter in a more general context.

FIGS. 10-12 present alternate embodiments for resonant converters thatuse extended topologies.

DETAILED DESCRIPTION

The following presents examples of multi-level hybrid DC to DCconverters that can operate at or near the converter's resonant pointacross a wide range of input and output levels. A first set ofembodiments use an LLC resonant converter topology, but where the seriesconnected LLC elements are driven by a hybrid combination of a two-statewaveform from one end and a multi-state (i.e., more than two states)waveform from the other end. The DC converter circuit regulates theoutput voltage by varying the duty cycle of the multi-state waveform,while maintaining the frequency of the waveforms at or near the resonantpoint, resulting in high efficiency of operation. The embodiments ofmulti-level hybrid converters presented can be used across a wide rangeof voltage levels, including high voltage levels. For example, they canbe applied to power supply systems requiring a regulated output voltagelevel. Particular examples can include battery charging circuits withinput and output voltages that can be in the range of several hundredvolts, such a battery charger for use with an electrical vehicle, wherethe input voltages could be in the 680-800 volt range and the outputcould be in the 400-750 volt range. These applications are by way ofexample only, and it is understood that the multi-level hybridconverters of the present technology may be used in other applications.

FIG. 2A shows a first embodiment of the multi-level hybrid resonantconverter system 180, including a control block 190 as well as a hybridresonant converter 100. The hybrid resonant converter 100 is connectedto a DC voltage source Vin 107 and generates a DC output voltage V_(O)at an output node (also labelled as V_(O)) that can be connected todrive a resistive load RL 109. The hybrid resonant convert 100 isconnected to receive a set of control signals from the control block 190that can be used to regulate the output voltage V_(O). The circuit ofthe control block 190 is connected to receive the DC output voltageV_(O) and the DC input voltage Vin. The control block 190 can beadjusted, such as by user input, to generate control signals that thehybrid resonant converter system 180 uses to regulate the output voltagelevel V_(O) relative to the input voltage level Vin.

FIG. 2B presents one embodiment for a multi-level hybrid resonantconverter circuit 100. In this embodiment of the multi-level hybridresonant converter circuit 100, the transformer T 102 has a secondarywinding 103 with a center tap c connected to drive the load, representedby the resistance RL 109, with the output voltage V_(O). The center tapc is also connected to ground through the capacitor 105. The upper andlower taps of the secondary winding 103 are connected to the circuitslow voltage level (here referred to as ground) though the switch S1 151on the one end and through the switch S2 152 on the other. The switchesS1 151 and S2 152 can be implemented as diodes in some embodiments.Active switching, or synchronous rectification, can also be used toreduce conduction loss, with the switches S1 151 and S2 152 beingimplemented as MOSFETs in some embodiments. To take the example of abattery charger application, the resistance RL 109 represents the loadof the battery or batteries being charged and V_(O) is the regulatedcharging voltage.

On the primary side to the left of the transformer T 102 in FIG. 2B, theLLC elements of a resonant tank 195 are the inductors Lr 131 and Lm 133and the capacitor Cr 135 that are connected in series between the node aand the node b. The inductor Lm 133 is connected in parallel with theprimary winding 101 of the transformer T 102. In this example, theinductor Lm 133 is connected through the capacitor Cr 135 on the oneside, and on the other side to the node a through the inductor Lr 131,but other series arrangements of the LLC elements can be used in otherembodiments.

The switches Q5 145 and Q6 146 form one embodiment of a first bridgecircuit, Bridge B 193. The node b is connected to ground through theswitch Q6 146 and to the high value of an input voltage through theswitch Q5 145, where the input voltage is represented as the voltagesupply Vin 107. As described further below, the switches Q5 145 and Q6146 generate a two-state waveform at the node b that is at or near theresonant frequency of the resonant tank 195. This will be similar to thesort of operation described above with respect to FIGS. 1A and 1B, butcan use a fixed frequency as the voltage level of the output V_(O) thatcan be regulated by varying the duty cycle of the waveform at node a. Insome embodiments, the switches Q5 145 and Q6 146 are implemented asMOSFETs.

An embodiment for a second bridge structure Bridge A 191 is formed bythe switches Q1 141, Q2 142, Q3 143, and Q4 144. The resonant converter100 is a hybrid converter in that, although node b uses a two-statewaveform generated by Bridge B 193, node a uses a multi-state waveformgenerated by Bridge A 191 using the switches Q1 141, Q2 142, Q3 143, andQ4 144 from the high and low values of the input voltage and anintermediate voltage level, such as can be provided by a voltagedivider. One embodiment for the voltage divider is given by thecapacitors 115 and 117. Node a is connected through Q3 143 and Q4 144 toan intermediate voltage node M of a voltage divider formed by thecapacitors 115 and 117, which in turn are connected in series betweenVin 107 and ground. In the examples here, the capacitors 115 and 117 aretaken to have the substantially equal (i.e., within a few percentage)capacitance values so the intermediate voltage node will be at Vin/2.The node a is connected to Vin 107 through switch Q1 141 and to groundthrough switch Q2 142. Although in the examples discussed here thecapacitors 115 and 117 are taken with the same capacitance so that theintermediate node M is at or near Vin/2, other voltage values can beobtained at the intermediate node M if wanted, by varying the relativecapacitances in the voltage divider.

FIG. 2C is a block diagram of an embodiment for control circuit block190 to provide the switching waveforms for controlling the switchesQ1-Q6 141-146 for the multi-level hybrid resonant converter system 180.In some embodiments, the switches Q1-Q6 141-146 can be implemented asMOSFETs. The control signal waveforms V_(Q1), V_(Q2), V_(Q3), V_(Q4),V_(Q5) and V_(Q6) generated for the switches are selected to providesoft switching for the power semiconductors under all operation range.(For the embodiments discussed below with respect to FIGS. 10-12, thecontrol circuitry would similarly provide the additional control signalsV_(Q7), V_(Q8), V_(Q9), V_(Q10), V_(Q11) and V_(Q12).) On the primaryside, switcher Q1-Q6 141-146 have zero voltage switching (ZVS) and, onthe secondary side, the switches 51 151 and S2 152 have zero currentswitches (ZCS). By varying the duty cycle on switches Q1-Q4 141-144while maintaining the frequency of the control waveforms for theseswitches, the LLC resonant converter 100 can operate at the resonantpoint of the resonant tank 195 for a wide operation range. The controlcircuit 190 can have both Vin and V_(O) as inputs to determine theappropriate switching waveforms to obtain the desired V_(O)/Vin ratio,where user input, which can come from other elements in a larger systemor by direct control, can be used to set the ratio of V_(O) to Vin.

FIG. 2D shows the waveforms at nodes a and b respectively generated byBridge A 191 and Bridge B based on a set of control waveforms fromcontrol circuit 190 for a switching sequence, such as illustrated belowwith respect to FIG. 3. At the top, FIG. 2D shows Va, the multi-statewaveform 201 (three-state in the examples here) at the Bridge A 191voltage point of node a which has the high value Vin, intermediate valueVin/2, and low value of ground. The levels correspond to the + terminalof the Vin voltage source 107, the intermediate node M of the voltagedivider between 115 and 117, and the − terminal (or ground) of Vin 107,where node a is respectively connected to these levels by switches pairs(Q1 141, Q3 143) and (Q4 144, Q2 142), as described further with respectto FIG. 3. In other embodiments, multi-state waveforms with more thanthree states can be used by using a different bridge structure. At thebottom, FIG. 2D has the 2-state waveform 203 of Vb, being either at thelevel corresponding to the + terminal of the Vin voltage source 107 orthe − terminal (or ground) of Vin 107. The switching sequence canoperate near or at the DC to DC converter's resonant frequency toachieve the best efficiency of operation, while control of the dutycycle for the switches Q1-Q4 141-144 is used to regulate the outputvoltage Vo.

FIG. 3 shows one embodiment for the set of control waveforms V_(Q1),V_(Q2), V_(Q3), V_(Q4), V_(Q5) and V_(Q6) for the switches Q1-Q6 141-146to generate the Va and Vb waveforms of FIG. 2D. Staring at the bottom ofFIG. 3, this shows that the control voltages V_(Q5) and V_(Q6) for theswitches Q5 145 and Q6 146 are non-overlapping and both have a fixedduty cycle of 0.5. When the control waveform V_(Q6) is high, Q6 146 ison and Vb is at its low state; and when the control waveform V_(Q5) ishigh, Q5 145 is on and Vb is at its high state. For the representationshown here, these are arranged such that switch Q6 146 is on during thefirst half cycle and switch Q5 145 is on in the second half cycle. Theresultant two-state Vb waveform on node b is shown as the bottom trace203 of FIG. 2D.

To generate the three-level waveform at node a, switches Q1 141 and Q2142 respectively turn on at the start of the first and second halfcycles, both having the same duty cycle D (or, more generally,substantially the same, where these differ by a few percent, +/−10% forexample) which can range from 0 to 0.5. Switch Q3 143 has a switchingwaveform V_(Q3) that is non-overlapping with V_(Q1) for switch Q1 141;and switch Q4 144 has a switching waveform V_(Q4) that isnon-overlapping with V_(Q2) for switch Q2 142. Switches Q3 143 and Q4144 consequently have substantially the same duty cycles of (1-D), asillustrated in the top and middle parts of FIG. 3.

The resultant Bridge A 191 voltage point waveform Va is the multi-statewaveform of the top trace 201 in FIG. 2D. Under this arrangement,

V _(O) /Vin=2D+(1−2D)/2=(1+2D)/2,

so that V_(O) can be regulated by varying D over the range 0-0.5 togenerate a ratio of V_(O)/Vin=0.5-1. The examples here are discussed inthe context of a fixed frequency in order to maintain efficiency;however, if desired, the waveforms can also have a variable frequencyif, for example, a wider range of V_(O)/Vin ratios is wanted. Note thatin the limiting cases of D=0, Va is just flat at Vin/2 and Vo=1/2 Vin;and for D=0.5, Va will become a two state waveform as for Vb, butoff-set half a cycle, and Vo=Vin. Under the switching sequenceillustrated in FIG. 3, at all input voltage ranges and all loadconditions, the circuit achieves zero voltage switching (ZVS) for all ofthe primary side MOSFET switches (Q1-Q6) and zero current switching(ZCS) for switches S1 151 and S2 152 on the secondary side. Thefrequency is again taken to be at or near the circuit's resonantfrequency.

Considering one embodiment for implementation, the switches Q1 141, Q2142, Q5 145 and Q6 146 are connected between one of either node a ornode b on one side, and to either ground or Vin on the other side. Theseswitches voltage clamp to Vin and can use, for example, 100V MOSFETs.The switches S1 151 and S2 152 on the secondary side voltage clamp to2Vo and can be implemented as 40V devices. The switches Q3 143 and Q4144, that connect node a to the mid-level voltage, clamp to Vin/2 andcan be implemented as 60V MOSFETs. Referring back to FIG. 3, in such anembodiment during the duration of duty cycle D, two of the 100V MOSFETsconduct. During the rest of the cycle with a duration of 0.5-D, two 60VMOSFETs and one 100V MOSFET conduct.

FIGS. 4A-4D and 5A-5D are additional simulated waveforms for the circuitof FIG. 2B, but for different combinations of Vin and V_(O). For FIGS.4A-4D, Vin=600V and V_(O)=400V. In FIG. 4A, the voltages Va and Vb atthe nodes a and b are shown at respective traces 401 and 403. For a Vinof 600V and a regulated V_(O) of 400V, D=1/6 and Va in trace 401 is atVin/2 twice as long as the low or high value. FIGS. 4B-4D respectivelyshow the current ILr 411 through Lr 131 and the current ILm4 11 throughLm 133 at full load (FIG. 4B), half load (FIG. 4C) and 10% load (FIG.4D). Under a full load (FIG. 4B), the current 411 through Lr 131 isrelatively sinusoidal, and the current 413 through Lm 133 is relativelyflat with a linear rise and fall, as a greater amount of current flowsthrough the primary coil of the transformer and is delivered to theload. As the load decreases to half load (FIG. 4C) and 10% load (FIG.4D), so that less current is drawn by the primary coil 101, the currentsILm 423 and ILm 433 in FIGS. 4C and 4D, respectively, through Lm 133increase closer to the currents ILr 421 and ILr 431, respectively,through Lr 131.

In FIGS. 5A-5D, Vin=800V and V_(O=)400V. For FIG. 5A, V_(O=)1/2Vin andD=0, so that Va is flat at 1/2 Vin, as shown at 501, while Vb is stillthe two-state waveform 503. Consequently, in this limit the circuit ofFIG. 2B tends to a two-state mode. The next three sets of traces (FIGS.5B-5D) underneath again show the current ILr 511 through Lr 131 and thecurrent ILm 511 through Lm 133 at full load (FIG. 5B, respectively 511,513), half load (FIG. 5C, respectively 521, 523) and 10% load (FIG. 5D,respectively 531, 533). For this V_(O)/Vin ratio, the current through Lr131 stays relatively sinusoidal, but as the load decreases less currentis drawn by the primary coil 101 of the transformer T 102 and morecurrent flows through Lm 133, with ILm 511 more closely tracking ILr513.

FIG. 6 shows another set of simulation waveforms, in this case forVin=680V and V_(O=)400V. The Va and Vb waveforms (respectively 601, 603)are respectively in the first and second waveform, showing a relativelysmall, but non-zero duty cycle. The current waveform 605 through Lr 131(middle waveform) and the current waveform 607 (fourth waveform) throughLm 133 are again shown, along with the current IR (bottom) with waveform609 supplied to the load RL 109. This example is at or near full load,so that ILm is relatively flat and the variation of ILr 605 is largelysent through the primary coil 101 of the transformer T 102. On thesecondary side, the current is the delivered to the load as shown by theIR waveform 609 at bottom.

FIG. 7 is flow chart illustrating the operation of the system of FIGS.2A-2D. At 701 the input voltage Vin received. To generate V_(O) fromVin, at 703 the control circuity generates the 2-state waveform at thefirst bridge (Bridge B 193) for node b and the multi-state waveform fornode a at the second bridge (Bridge A 191), as described above withrespect to FIG. 3. The waveforms are received at the resonant tank 195of Lr 131, Lm 133, and Cr 135 at 705, generating the output voltageV_(O) for the load at 707. The output voltage V_(O) is regulated at 709by continuing to operate at or near the resonant frequency (such aswithin a few percent, within +/−10% for example), but varying the dutycycle used to generate the waveform at node a. The duty cycle can bevaried as described above with respect to FIG. 3 to keep the V_(O)/Vinratio regulated to provide the desired V_(O) across a range of Vinvalues.

FIGS. 8A provides a generalization of the hybrid resonant converter ofFIG. 2B. In such embodiments for a DC to DC voltage converter 100, theLLC section of Lr 131, Lm 133 and Cr 135 can be replaced as shown inblock 805 by a more general resonant tank of combinations of inductorsand capacitances (such as LC, LCL, LCLC and so on), or with a pulsewidth modulation (PWM) inductor, such as a single inductor orcombination of one or more inductors and DC blocking capacitors. Ineither case, the resonant tank or PWM inductor 805 is connected betweenBridge B 803 and Bridge A 801, with an inductor in parallel with theprimary coil 101. Bridge B 803 is a generalization of switches Q5 145and Q6 146 that provides a two level (either level 1 on the top rail ofVin or level 2 on the bottom rail of ground) to the upper input node ofthe resonant tank or PWM inductor 805. Bridge A 801 is a generalizationof the switches Q1-Q4 141-144 and provides a three level (level 1, level2 or level 3 of 1/2 Vin at the intermediate node M) to the lower inputnode of the resonant tank or PWM inductor 805. As described above withrespect to FIGS. 2-7, the output voltage V_(O) provided by outputsection 809 can be regulated by varying the duty cycle within Bridge A801.

In other embodiments Bridge B can also generate a 3-level waveform forthe upper input of the resonant tank or PWM inductor 805, as illustratedin FIG. 9A for Bridge B 833. In embodiments of FIG. 9A, Bridge A 801 andthe other elements can have a similar structure to embodiments describedwith respect to FIG. 9A. Unlike FIG. 9A, in FIG. 9B Bridge B 833 is nowalso connected to the intermediate node M to receive the intermediatevoltage level. This allows for Bridge B 833 to also provide amulti-state waveform to the resonant tank or PWM inductor 805.

FIG. 10 shows an example of an embodiment where both bridge circuits use3-level waveforms. Relative to FIG. 2B, the embodiment of FIG. 10 addsan additional pair of switches Q7 147 and Q8 148 that can be implementedas MOSFETs, similar to as described above for Q3 143 and Q4 144, withcontrol signals V_(Q7) and V_(Q8). The inclusion of Q7 147 and Q8 148allow for a multi-state waveform to also be applied to node b, wherethis can be generated by switches Q5-Q8 145-148 analogously to thegeneration of Va by Q1-Q4 141-144 as described with respect to FIG. 3.By using a variable duty cycle D″ for Q5-Q8 145-148 that is independentof the duty cycle D for Q1-Q4 141-144, the V_(O)/Vin range can beextended to from 0 to 1 by additionally varying D″ as well as D.

All of the embodiments described so far have included isolation, wherethe input is connected to the output through the transformer T 102 toisolate any DC offset from the input side. This is illustrated in FIGS.8A and 9A, where the input side is connected to the primary coil 101 oftransformer T 102, and the output side is connected to the secondarycoil 103. It is also possible to provide embodiments without isolation,where the output is connected to the resonant tank without theintervening transformer. This illustrated in the embodiments of FIGS. 8Band 9B, which correspond to FIGS. 8A and 9A respectively, but withoutthe isolation provided by the transformer T 102.

In FIG. 8B, the transformer T 102 of FIG. 8A is removed. Rather thanhaving an output node connected to the intermediate circuit of theresonant tank or PWM inductor 805 through the transformer T 102 as inFIG. 8A, in FIG. 9B the output or load 821 is now connected to theresonant tank or PWM inductor 805 without isolation. In the example ofFIG. 8B, the output or load 821 is connected through the resonant tankor PWM inductor 805 to Bridge B 803 on the one side, and connected toBridge A 801 on the other side. The load can, for example, be aresistive load such as a battery or a combination of a resistive loadand rectifiers. The current though the load would then correspond to theload through the primary coil 101 in FIG. 8A.

Similarly, in FIG. 9B relative to FIG. 9A, the transformer T 102 of FIG.9A is removed. In this example, the output node or load 821 is againconnected the three level Bridge A 801 and three level Bridge B 833. Theintermediate circuit of the resonant tank or pulse width modulation(PWM) inductor 805, such as a single inductor or combination of aninductor and a DC blocking capacitor, is connected between Bridge B 833and the load 821. The current though the load would then correspond tothe load through the primary coil 101 in FIG. 9A.

In each of the embodiments of FIGS. 8A, 8B, 9A and 9B, Bridge A 801generates a three-level waveform, such as shown at 201 for Va in FIG.2D. In other embodiments, multi-state bridge circuits with more thanthree states can be used. Similarly, although Bridge B 833 of FIGS. 9Aand 9B generates a three-level waveform, multi-state bridge circuitswith more than three states can be used in other embodiments.

Considering FIGS. 8A, 8B, 9A, and 9B, the DC to DC converters of thesefigures includes a first bridge circuit module (Bridge A 801) that isconnected between the + and − terminals of the input voltage source 107and also to an intermediate voltage level. In this example, theintermediate voltage level is provided by an intermediate node M of thevoltage divider of capacitors 115 and 117, which are also connectedbetween the + and − terminals of the input voltage source 107, but, moregenerally, other means can provide this intermediate voltage level. Thebridge circuits then generate the multi-state waveform applied to theresonant tank or load. Specific arrangements of switches and diodes areused in the examples presented here; but other multi-state bridgestructures composed of switches, diodes or other means can also be used.Similarly, for Bridge B, although specific examples are illustratedhere, more generally other means composed of switches, diodes or othercircuit elements can also be used to provide either a two-state ormulti-state bridge structure.

The embodiment used here for a resonant tank is an LLC structure whosecomponents are arranged in a particular configuration, but otherresonant tank or pulse width modulation (PWM) inductor structures orsimilar means can be used. The load can be connected either through atransformer, as in FIGS. 8A and 9A, or without isolation from atransformer or other isolation means, as in FIGS. 8B or 9B. As discussedwith respect to FIGS. 8B or 9B, the load can be resistive, a combinationof a resistive load and rectifiers, or other load types.

In FIGS. 8A and 9A, the output section 809 can use a secondary coil witha center tap c and a pair of diode or switches S1 151 and S2 152 asshown in FIG. 2B, but other forms and arrangements of secondary coils,switches, diodes or other means can be used to drive the load on theoutput side. FIGS. 11 and 12 are alternate embodiments using extendedtopologies, again in a hybrid arrangement providing a two-state waveform on node b and a multi-state waveform on node a, but with alternatestructures for Bridge A 801.

FIGS. 11 and 12 present embodiments similar to that of FIG. 2B, but areextended embodiments with variations on the bridge providing thewaveform on node a. The variation of FIG. 11 repeats many of theelements of FIG. 2B, but uses a neutral point clamping for theconnection for node a. More specifically, in FIG. 11 switches Q5 145, Q6146, the LLC resonant tank (Lr 131, Lm 133 and Cr 135), transformer T102, and the switches S1 151, S2 152 and the other elements on thesecondary side where the load is connected are all as in FIG. 2B. Node ais now connected to Vin through the series connected switches Q1 141 andQ9 161, where the node between these two switches is connected to theintermediate voltage node though the diode D3 163, which is oriented toallow current to flow from the intermediate voltage node. On the otherside, node a is also now connected to ground through the seriesconnected switches Q2 142 and Q10 162, where the node between these twoswitches is connected to the intermediate voltage node though the diodeD4 164 which is oriented to allow current to flow to the intermediatevoltage node. Relative to FIG. 2B's switches Q1 141 and Q2 142, in FIG.11 MOSFETs with a lower voltage rating can be used for switches Q1 141,Q2 142, Q9 161 and Q10 162 as the voltage drop between node a and thesupply level is now across a pair of switches in both directions. Thecontrol signals for Q9 161 and Q10 162 are represented at V_(Q9) andV_(Q10).

In FIG. 11, the use of the diodes D3 163 and D4 164 can leave the nodebetween Q1 141 and Q9 161 on the one side of node a, and the nodebetween Q2 142 and Q10 162 on the other side of node a, to float. Theembodiment FIG. 12 has a similar topology to FIG. 11, but with thediodes D3 163 and D4 164 respectively replaced by the switches Q11 165and Q12 166 that are controlled with respective control signals V_(Q11)and V_(Q12). This allows for more control of the voltage level on thenode between Q1 141 and Q9 161 and on the node between Q2 142 and Q10162, as the switches Q11 165 and Q12 166 respectively allow these nodesto be clamped to the level on the intermediate voltage node M. Theswitches Q11 165 and Q12 166 can be implemented as MOSFETs. AlthoughFIGS. 11 and 12 are again described for a hybrid arrangement of athree-level waveform on node a and a two-level waveform on node b,either of the corresponding bridge structures can use waveforms ofhaving higher numbers of levels.

It is understood that the present subject matter may be embodied in manydifferent forms and should not be construed as being limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this subject matter will be thorough and complete and will fullyconvey the disclosure to those skilled in the art. Indeed, the subjectmatter is intended to cover alternatives, modifications and equivalentsof these embodiments, which are included within the scope and spirit ofthe subject matter as defined by the appended claims. Furthermore, inthe following detailed description of the present subject matter,numerous specific details are set forth in order to provide a thoroughunderstanding of the present subject matter. However, it will be clearto those of ordinary skill in the art that the present subject mattermay be practiced without such specific details.

Aspects of the present disclosure are described herein with reference toflowchart illustrations and/or block diagrams of methods, apparatuses(systems) and computer program products according to embodiments of thedisclosure. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer program instructions executed by the control circuit elements.These computer program instructions may be provided to a processor of ageneral purpose computer, special purpose computer, or otherprogrammable data processing apparatus to produce a machine, such thatthe instructions, which execute via the processor of the computer orother programmable instruction execution apparatus, create a mechanismfor implementing the functions/acts specified in the flowchart and/orblock diagram block or blocks.

The description of the present disclosure has been presented forpurposes of illustration and description, but is not intended to beexhaustive or limited to the disclosure in the form disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of thedisclosure. The aspects of the disclosure herein were chosen anddescribed in order to best explain the principles of the disclosure andthe practical application, and to enable others of ordinary skill in theart to understand the disclosure with various modifications as aresuited to the particular use contemplated.

The disclosure has been described in conjunction with variousembodiments. However, other variations and modifications to thedisclosed embodiments can be understood and effected from a study of thedrawings, the disclosure, and the appended claims, and such variationsand modifications are to be interpreted as being encompassed by theappended claims. In the claims, the word “comprising” does not excludeother elements or steps, and the indefinite article “a” or “an” does notexclude a plurality.

For purposes of this document, it should be noted that the dimensions ofthe various features depicted in the figures may not necessarily bedrawn to scale.

For purposes of this document, reference in the specification to “anembodiment,” “one embodiment,” “some embodiments,” or “anotherembodiment” may be used to describe different embodiments or the sameembodiment.

For purposes of this document, a connection may be a direct connectionor an indirect connection (e.g., via one or more other parts). In somecases, when an element is referred to as being connected or coupled toanother element, the element may be directly connected to the otherelement or indirectly connected to the other element via interveningelements. When an element is referred to as being directly connected toanother element, then there are no intervening elements between theelement and the other element. Two devices are “in communication” ifthey are directly or indirectly connected so that they can communicateelectronic signals between them.

For purposes of this document, the term “based on” may be read as “basedat least in part on.”

For purposes of this document, without additional context, use ofnumerical terms such as a “first” object, a “second” object, and a“third” object may not imply an ordering of objects, but may instead beused for identification purposes to identify different objects.

The foregoing detailed description has been presented for purposes ofillustration and description. It is not intended to be exhaustive or tolimit the subject matter claimed herein to the precise form(s)disclosed. Many modifications and variations are possible in light ofthe above teachings. The described embodiments were chosen in order tobest explain the principles of the disclosed technology and itspractical application to thereby enable others skilled in the art tobest utilize the technology in various embodiments and with variousmodifications as are suited to the particular use contemplated. It isintended that the scope be defined by the claims appended hereto.

Although the subject matter has been described in language specific tostructural features and/or methodological acts, it is to be understoodthat the subject matter defined in the appended claims is notnecessarily limited to the specific features or acts described above.Rather, the specific features and acts described above are disclosed asexample forms of implementing the claims.

What is claimed is:
 1. A direct current to direct current (DC to DC)voltage converter, comprising: an input voltage node configured toreceive an input voltage; a first bridge circuit connected to the inputvoltage node and a ground node, and configured to provide a firstwaveform to a first internal node; a second bridge circuit connected tothe input voltage node, an intermediate voltage node and the groundnode, and configured to provide a second waveform to a second internalnode, the second waveform being a multi-state waveform; and anintermediate circuit including a first inductor connected between thefirst internal node and the second internal node, the first inductorconfigured to be driven by the first and second waveforms to provide anoutput voltage to an output voltage node.
 2. The DC to DC converter ofclaim 1, further comprising: a transformer having a primary coil and asecondary coil with a common core, wherein the output voltage node isconnected to a first terminal of the secondary coil, and wherein thefirst inductor is connected in parallel with the primary coil.
 3. The DCto DC converter of claim 2, wherein the intermediate circuit is aresonant tank.
 4. The DC to DC voltage converter of claim 3, whereinresonant tank comprises: the first inductor, a second inductor and afirst capacitor connected in series between the first internal node andthe second internal node.
 5. The DC to DC voltage converter of claim 1,wherein the first bridge circuit comprises: a first switch connectedbetween the first internal node and the input voltage node; and a secondswitch connected between the first internal node and the ground node. 6.The DC to DC voltage converter of claim 5, wherein the second bridgecircuit comprises: a third switch connected between the second internalnode and the input voltage node; a fourth switch connected between thesecond internal node and the ground node; and an intermediate voltageswitch connected between the intermediate voltage node and the secondinternal node.
 7. The DC to DC voltage converter of claim 6, wherein theintermediate voltage switch comprises a fifth switch and a sixth switchconnected in series between the intermediate voltage node and the secondinternal node.
 8. The DC to DC voltage converter of claim 6, wherein theintermediate voltage switch comprises: a fifth switch through which thethird switch is connected to the second internal node through a thirdinternal node; a sixth switch through which the fourth switch isconnected to the second internal node through a fourth internal node; afirst diode connected between the third internal node and theintermediate voltage node; and a second diode connected between thefourth internal node the intermediate voltage node.
 9. The DC to DCvoltage converter of claim 6, wherein the intermediate voltage switchcomprises: a fifth switch through which the third switch is connected tothe second internal node through a third internal node; a sixth switchthrough which the fourth switch is connected to the second internal nodethrough a fourth internal node; a seventh switch connected between thethird internal node and the intermediate voltage node; and an eighthswitch connected between the fourth internal node the intermediatevoltage node.
 10. The DC to DC voltage converter of claim 1, furthercomprising: a control circuit connected to the first bridge circuit andthe second bridge circuit and configured to supply thereto a set ofcontrol signals having a cycle of a first frequency, wherein the controlcircuit is configured to supply a set of control signals whereby thefirst bridge circuit generates the first waveform to have the firstfrequency and to have at least a high value and a low value, whereby thesecond bridge circuit generates the second waveform to have the firstfrequency and to have at least a high value, an intermediate value and alow value, and wherein the first and second internal nodes are notconcurrently at either of the corresponding high values or thecorresponding low values.
 11. The DC to DC voltage converter of claim10, wherein control circuit is configured to provide to the secondbridge circuit control signals having an adjustable duty cycle, andwherein control circuit is further configured to regulate the value ofthe output voltage by varying a duration of the duty cycle whilemaintaining the first frequency.
 12. A direct current to direct current(DC to DC) voltage conversion system, comprising: a DC to DC conversioncircuit, comprising: an input voltage node; a first bridge circuitconnected to the input voltage node and a ground node, and configured toprovide a first waveform to a first internal node; a second bridgecircuit connected to the input voltage node, an intermediate voltagenode and the ground node, and configured to provide a second waveform toa second internal node, the second waveform being a multi-statewaveform; and an intermediate circuit including a first inductorconnected between the first internal node and the second internal node,the first inductor configured to be driven by the first and secondwaveforms to provide an output voltage to an output voltage node; and acontrol circuit connected to the first bridge circuit and the secondbridge circuit and configured to supply thereto a set of control signalshaving a cycle of a first frequency, wherein the control circuit isconfigured to supply a set of control signals to the DC to DC conversioncircuit whereby the first bridge circuit applies to the first internalnode the first waveform of the first frequency and having at least ahigh value and a low value, whereby the second bridge circuit applies tothe second internal node the second waveform having at least a highvalue, an intermediate value and a low value, and wherein the first andsecond internal nodes are not concurrently at either of thecorresponding high values or the corresponding low values.
 13. The DC toDC voltage conversion system of claim 12, wherein the control circuit isconfigured to provide to the second bridge circuit control signalshaving an adjustable duty cycle.
 14. The DC to DC voltage conversionsystem of claim 13, wherein the control circuit is further configured toregulate a value of the output voltage by varying a duration of theadjustable duty cycle while maintaining the first frequency.
 15. Amethod of generating a direct current (DC) output voltage from a DCinput voltage, comprising: receiving an input voltage; generating afirst waveform from the input voltage; generating a second waveform fromthe input voltage; receiving the first waveform and the second waveformat a first node and a second node, respectively, of a DC to DC voltageconverter, the DC to DC voltage converter comprising: a resonant tankconnected between the first node and the second node; and an outputvoltage node connected to the resonant tank; and generating by the DC toDC voltage converter from the first and second waveforms of an outputvoltage at the output voltage node, wherein the first waveform has acycle of a first frequency with a high value in a second part of thecycle and a low value in a first part of the cycle, and wherein thesecond waveform is a multi-level waveform of the first frequency withthe high value for a first portion of the first part of the cycle and anintermediate value for a second portion of the first part of the cycle,and with the low value for a first portion of the second part of thecycle and the intermediate value for a second portion of the second partof the cycle, the intermediate value being between the high value andthe low value.
 16. The method of claim 15, wherein the first portion ofthe part of the cycle is of substantially the same duration as the firstportion of the second part of the cycle.
 17. The method of claim 15,further comprising: regulating a value of the output voltage by varyinga duration of the first portion of one or both of the first part of thecycle or the second part of the cycle while maintaining the firstfrequency.
 18. The method of claim 15, wherein generating the secondwaveform comprises: receiving first, second, third and fourth controlwaveforms at first, second, third, and fourth switches, respectively,wherein the first switch is connected between the input voltage and thesecond node, the second switch is connected between ground and thesecond node, and the third and fourth switches are connected in seriesbetween the second node and an intermediate node configured to supplythe intermediate value.
 19. The method of claim 18, wherein the firstand third control waveforms are non-overlapping, the first controlwaveform being high during the first portion of the second part of thecycle, and wherein the second and fourth control waveforms arenon-overlapping, the second control waveform being high during the firstportion of the first part of the cycle.
 20. The method of claim 18,wherein the first and second control waveforms have substantially equalduty cycles, the method further comprising: regulating a value of theoutput voltage, the regulating including varying durations of the dutycycles of the first and second control waveforms while maintaining thefirst frequency.